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Thursday, 1 February 2018

MTech VLSI 2015 2016 Live Projects

MTech VLSI 2015 2016 Live Projects

Find the below 2015-2016 IEEE VLSI Projects List for ME/M.Tech Final Year Students. Here Student can select any project Title., Our VLSI Developers has developed projects as per the journal paper. We can provide Abstract, Project Source Code, Documentation, PPT Presentation and Execution Support. Contact us for more details.
We Provide Journal Projects and solutions for B.Tech, M.Tech and Research, We can provide solution for any paper and develop the code with an extension., If you have selected any paper then Feel free to share your idea with us.


  1. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
  2. Variable Latency Speculative Han-Carlson Adder
  3. An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes
  4. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
  5. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
  6. Design and Analysis of Approximate Compressors for Multiplication
  7. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
  8. Low-Power Programmable PRPG with Test Compression Capabilities
  9. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
  10. Recursive Approach to the Design of a Parallel Self-Timed Adder
  11. Efficient Coding Schemes for Fault-Tolerant Parallel Filters
  12. High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations
  13. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
  14. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability
  15. A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders
  16. Trade-Offs for Threshold Implementations Illustrated on AES
  17. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
  18. Reliable and Error Detection Architectures of Pomaranch for False-AlarmSensitive Cryptographic Applications
  19. A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT
  20. Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT
  21. Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
  22. Advanced Low Power RISC Processor Design using MIPS Instruction Set
  23. Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures


1High – Throughput Finite Field Multipliers Using Redundant Basis For Fpga And Asic Implementations2015
2A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of   Dct2015
3Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes2015
4Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For Dsrc Applications2015
5Obfuscating Dsp Circuits Via High-Level Transformations2015
6Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding2015
7An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm For Reconfigurable Fir Filter Synthesis2015
8Flexible Dsp Accelerator Architecture Exploiting Carry-Save Arithmetic2015
9Low-Latency High-Throughput Systolic Multipliers Over For Nist Recommended Pentanomials2015
10A Synergetic Use Of Bloom Filters For Error Detection And Correction2015
11Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block2015
12Recursive Approach To The Design Of A Parallel Self-Timed Adder2015
13Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic2015
14Efficient Sub Quadratic Space Complexity Architectures For Parallel Mpb Single- And Double-Multiplications For All Trinomials Using Toeplitz Matrix-Vector Product Decomposition2015
15Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications2015
16Fast Sign Detection Algorithm For The Rns Moduli Set {2n+1 − 12− 12n}2015
17Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks2015
18Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures2015
19Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT Processors2015
20VLSI Computational Architectures For The Arithmetic Cosine Transform2015
21A Generalization Of Addition Chains And Fast Inversions In Binary Fields2015
22Low-Power And Area-Efficient Shift Register Using Pulsed Latches2015
23Communication Optimization Of Iterative Sparse Matrix – Vector Multiply On GPUs And FPGAs2015
24A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems2015
25Low-Power Programmable PRPG With Test Compression Capabilities2015
26One Minimum Only Trellis Decoder For Non – Binary Low – Density Parity – Check Codes2015
27A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic2015
28Mixing Drivers In Clock-Tree For Power Supply Noise Reduction2015
29A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-mW Energy Harvesting Applications2015
30Simplified Trellis Min–Max Decoder Architecture For Nonbinary Low-Density Parity-Check Codes2015
31New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication Without Pre-Computation2015
32Fault Tolerant Parallel Filters Based On Error Correction Codes2015
33Comments On “Low-Latency Digit-Serial Systolic Double Basis Multiplier Over GF (2m ) Using Subquadrat Ic Toeplitz Matrix- Vector Product Approach”2015
34Skewed-Load Test Cubes Based On Functional Broadside Tests For A Low-Power Test Set2015
35Low-Complexity Tree Architecture For Finding The First Two Minima2015
36Efficient Coding Schemes For Fault-Tolerant Parallel Filters2015
37Piecewise-Functional Broadside Tests Based On Reachable States2015
38A Multicycle Test Set Based On A Two-Cycle Test Set With Constant Primary Input Vectors2015
39Partially Parallel Encoder Architecture For Long Polar Codes2015
40Novel Block-Formulation And Area-Delay – Efficient Reconfigurable Interpolation Filter Architecture Formulti – Standard SDR Applications2015
41An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator2014
42Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip2014
43A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits2014
44Fast Radix-10 Multiplication Using Redundant BCD Codes2014
45A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values2014
46Multifunction Residue Architectures for Cryptography2014
47Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low
4832 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler2014
49Recursive Approach to the Design of a Parallel Self-Timed Adder2014
50Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications2014
51Statistical Analysis of MUX-Based Physical Unclonable Functions2014
52Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme2014
53Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation2014
54Efficient Integer DCT Architectures for HEVC2014
55Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm2014
56A Method to Extend Orthogonal Latin Square Codes2014
57Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter2014
58Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator2014
59On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays2014
60Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata2014
61Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding2014
62Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic2014
63Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes2014
64Area–Delay–Power Efficient Carry-Select Adder2014
65Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences2014
66Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement2014
67Digitally Controlled Pulse Width Modulator for On-Chip Power Management2014
68Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States2014
69Area-Delay Efficient Binary Adders in QCA2014
70Sharing Logic for Built-In Generation of Functional Broadside Tests2014

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