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Friday, 9 February 2018

M. Tech 2014-2015 VLSI Projects

M. Tech 2014-2015 VLSI Projects
S.NoProject TitlesYEAR / Month
001Low-Power and Area-Efficient Carry Select AdderJan 2014
002Design of Dedicated Reversible Quantum Circuitry for Square ComputationJan 2014
003Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal ProcessingJan 2014
004A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal ConverterJan 2014
005All Optical Reversible Multiplexer Design using Mach-Zehnder InterferometerJan 2014
006Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response FiltersJan 2014
007Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression SpaceJan 2014
008Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-DelayFeb 2014
009Low – Power Digital signal Processor Architecture for wireless sensor NodesFeb 2014
010Time-Based All-Digital Technique for Analog Built-in Self-TestFeb 2014
011Analysis and Design of a Low – voltage Low – Power Double Tail ComparatorFeb 2014
012A new hydrid  multiplier using Dadda and Wallace methodFeb 2014
013Parallel multiplier – accumulator based on radix- 2 modified Booth algorithm by using a VLSI architectureFeb 2014
014Fully Reused VLSI Architecture of FM0 / Manchester encodingUsing SOLS Technique for DSRC ApplicationsFeb 2014
015Reverse Converter Design Via Parallel – Prefix Adders: Novel Components, Methodlogy , and ImplementationsFeb 2014
016Bit – Level Optimization of Adder – Trees for Multiple Constant Multiplications for Efficient FIR Filter ImplementationFeb 2014
017Implementation of floating point MAC Using Residue Number SystemFeb 2014
0184-2 Compressor Design with New XOR-XNOR ModuleFeb 2014
019Realization of 2:4 reversible decoder and its applicationFeb 2014
020Novel Field _Programmable Gate Array Architecture for Computing the  Eigen Value  Decomposition of  Para – Hermitian Polynomial MatricesMar 2014
021Data Encoding Techniques for Reducing Energy Consumption  in Network _on _chipMar 2014
022Low-Complexity Low-Latency Architecture for Matching of Data Encoded with Hard Systematic Error – Correcting CodesMar 2014
023A Synergetic Use of  Bloom Filters For Error Detection and CorrectionMar 2014
024HIGH SPEED VEDIC MULTIPLIER DESIGNSA REVIEWMar 2014
025High- Throughput Multi Standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed ArithmeticMar 2014
026Quaternary Logic Lookup  Table in Standard CMOSMar  2014
027Universal Set of CMOS Gates for the Synthesis of  Multiple Valued Logic Digital CircuitsMar 2014
028Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1-1, 2n-1, 2n }Mar 2014
029Hardware Efficient Mixed Radix-25/16/9 FFT for LTE SystemsMar 2014
030VLSI Architecture Design of Guided Filter for 30 Frames/s Full-HD VideoMar 2014
031Novel Reconfigurable Hardware Architecture for Polynomial Matrix MultiplicationsApr 2014
032A 16-Core Processor With Shared-Memory and Message-Passing CommunicationsApr 2014
03332 Bit X 32 Bit  Multiprecision Razor- Based Dynamic Voltage Scaling Multiplier with Operands SchedulerApr 2014
034Multifunction Residue Architectures for CryptographyApr 2014
035Improved 8 –Point Approximate DCT for Image and Video Compression Requiring Only 14 AdditionsMay 2014
036Reliable Concurrent Error Detection Architectures for Extended Euclidean –Based Division Over $(rm GF} (2 ^{m})$May 2014
037Reconfigurable CORDIC – Based Low – Power DCT Architecture Based on Data PriorityMay 2014
038Area – Delay Efficient Binary  Adder in QCAMay 2014
039Low- Complexity Reconfigurable Fast Filter Bank  for Multi –Standard Wireless ReciversMay  2014
040Binary Division algorithm and high Speed Deconvolution algorithm (Based on Ancient Indian Vedic Mathematics)May  2014
041Design and Implementation of Modified Signed – Digit  AdderMay  2014
042A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix -2 FFTMay  2014
043Radix-2Arithmetic for Multiplication by a ConstantMay  2014
044Design of a Low-Voltage Low –DropOut RegulatorJune 2014
045Design and Analysis of Approximate Compressors for MultiplicationJune 2014
046Reviewing High –Radix Signed  – Digit AddersJune 2014
047Area – Delay – Power Efficient Carry –Select AdderJune 2014
048Method for designing Multi-Channel RNS Architectures to prevent  Power Analysis SCAJune 2014
049An Optimized Modified Booth Recoder for Efficient Design of the  Add- Multiply OperatorJuly 2014
050Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOSJuly 2014
051Precise VLSI Architecture for AI – Based 1-D/2-D Daub -6 Wavelet Filter Bank with Low Adder – CountJuly 2014
052A Method to Extend Orthogonal Latin Square CodesJuly 2014
053Low – Power Programmable PRPG With Test Compression CapabilitiesJuly 2014
054Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital FilterJuly 2014
055Novel Square root algorithm and its FPGA ImplementationJuly 2014
056High – Throughput Turbo Decoder with Parallel Architecture for LTE Wireless Communication StandardsAugu 2014
057Fast Radix -10 Multiplication Using Redunant BCDAugu2014
058A parallel radix –sort –based VLSI architecture for finding the first W maximum/minimum valuesAugu2014
059Performance Analysis of the  CS-DCSK /BPSK Communication SystemSep 2014
060VLSI Design of a Large – Number  Multiplier for  Fully – Homorphic EncryptionSep 2014
IEEE 2013  & 2012 Projects
S.NoProject TitlesYEAR
061High-Speed Low-Power Viterbi Decoder Design for TCM Decoders2013
062Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications2013
063Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code2012
064Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes2013
065Multi operand Redundant Adders on FPGAs2013
066Data Encoding Schemes in Networks on Chip2011
067A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm2012
068Design and Implementation of Multi-mode QC-LDPC Decode2010
069Data Encoding for Low-Power in Wormhole-Switched Networks-on- Chip2013
070Low Complexity Digit Serial Systolic Montgomery Multipliers For Special Class Of GF(2M)2013
071Split-path Fused Floating Point Multiply Accumulate (FPMAC).2013
072Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool.2013
073Low Power and Design Reed –Solomon Encoder2013
074A Spurious-Power Suppression Technique for Multimedia/DSP Applications (MAC)2011
075Digital Filter Implementation Based on the RNS with Diminished-1 Encoded Channel2012
076Low Power 64bit Multiplier Design by Vedic Mathematics2013
077VLSI implementation of Fast Addition using Quaternary Signed Digit Number System2013
078An Efficient High Speed Wallace Tree Multiplier2013
079Low Latency Systolic Montgomery Multiplier for finite Field GF (2m) Based on Pentanomials2013
080Radix-4 and radix-8 booth encoded multi-modulus multipliers2013
081Viterbi Based Efficient Test Data Compression2013
082CORDIC Designs for Fixed Angle of Rotation2013
083Product codes of MLC NAND  Flash  Memories2013
084Pipelined Parallel FFT Architectures via Folding Transformation2012
085High Speed Parallel Decimal Multiplication with Redundant Internal Encodings2013
086Scalable Digital CMOS Comparator Using a Parallel Prefix Tree2013
087Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM).2013
088New High-Speed Multioutput Carry Look-Ahead Adders2013
089Modulo 2n-2 Arithmetic Units2013
090A New RNS based DA Approach fo Inner Product Computation2013
091FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer2013
092Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA2013
093Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems2013
094A Single-Channel Architecture for Algebraic Integer Based 8 x 8 2-D DCT Computation2013
095Low Power and Design Reed –Solomon Encoder2013
096Design Of An On – Chip Permutation  Network For Multiprocessor Soc2013
097A Practical NoC Design for Parallel DES Computation2013
098Low-Power Logarithmic Number System Addition/Subtraction and their Impact on  Digital Filters2013
099Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme2012
100Constant Delay Logic2013
101Parallel AES Encryption Engines for Many- Core Processor Arrays.2013
102Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials2012
103VLSI Architecture of Arithmetic code used in SPHIT2012

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